The present invention relates to the field of electronic data processing devices, and more particularly, to the operation of a data processor.
Traditionally, a processor has had a single instruction set and could only accept operating systems and application programs in that instruction set. Thus, if a processor architecture and the instruction set were fundamentally altered, they would no longer be capable of executing the existing software base of operating systems and application programs. Therefore, fundamental changes, and therefore major advances in processor architecture and instruction sets, have generally not been possible where backward compatibility is an important design objective.
U.S. Pat. No. 5,638,525 (""525), assigned to Intel Corporation, describes a processor architecture capable of accepting multiple operating systems and applications programs using different instruction sets. This architecture allows a first program using a first instruction set to execute concurrently with a second program using a different instruction set that is not backward compatible with the first instruction set. One specific embodiment shown in the ""525 patent is a processor that can accept both a 32 bit instruction set and a 64 bit instruction set. In one example embodiment, the processor architecture of the ""525 patent operates in a separate mode for each different ISA. In one example embodiment, but not by way of limitation, a first mode may be a xe2x80x9cnativexe2x80x9d mode, wherein the processor can execute instructions of a first instruction set without any special pre-processing. In another mode, for example, instructions, typically of an older instruction set are translated to the native mode instruction set before decoding and execution.
In one embodiment illustrated in the ""525 patent, the processor executes instructions of a first instruction set, obtained from a first location in memory, until it encounters an instruction that specifies to the processor that it should branch to and begin processing instructions of a second, different, instruction set, stored in a different location in memory. When such a branch instruction is encountered, the processor transitions to the mode of operation corresponding to the second instruction set. If the processor uses a pipeline architecture, wherein instructions are processed in a series, or xe2x80x9cpipeline,xe2x80x9d of stages, with each instruction dwelling in a stage for one (or more) clock cycle(s), it may be necessary to first complete processing of the instructions from the first instruction set before beginning the execution of the instructions from the second instruction set. This means synchronizing the processor and having all the architectural states committed. This, in turn, may require that the pipeline be first flushed of all instructions from the first instruction set before instructions from the second instruction set are fed into the pipeline. Flushing instructions of one instruction set before beginning to execute instructions of a second instruction set introduces an undesirable delay. This delay may be worsened by the need to execute a set of transition instructions that set up the processor for operation in the mode to which it is switching. For these and other reasons, there is a need for the present invention.
The present invention provides a method and apparatus for speeding the transition from one instruction set mode to another in a multi-instruction set processor.